1. Field of the Invention
The present invention relates to the structures of a high withstand voltage MIS transistor and a complementary transistor, and a method for manufacturing the same.
2. Related Arts
Conventionally, explaining by using a P channel MOS type transistor as shown in FIG. 1 as an example, there exists a so-called "offset/gate structure transistor" in which the drain thereof is divided into two regions, one being a high impurity concentration (P.sup.+) region 7 and the other being an offset region 6 having a lower impurity concentration (P.sup.-) than that of the region 7, thereby suppressing the field concentration at a gate edge portion 9 and enhancing the drain voltage-withstand characteristic.
However, the above-mentioned offset/gate-structure element incurs the problem that while in operation, the offset region 6 acts as a high resistance component, thereby decreasing current-driving capacity.
In order to solve the above-mentioned problem, Published Unexamined Japanese Patent Application No. H42-12465 discloses a so-called duplex-offset structure transistor which is constructed as follows. As shown in FIG. 2, the offset region 6 and the drain region 7 of the conventional offset/gate structure transistor are surrounded by a diffusion layer region 10 of the same conductivity type as that of the substrate so as to enable the formation of an offset region 6 by a high impurity concentration diffusion layer. This offset region 6 is thereby made to have a lower resistance, which results in improvement of the current-driving capacity.
Further, in a CMOS type transistor, as the miniaturization thereof proceeds, the short-channel effect or hot-carrier effect thereof becomes large, and therefore consideration needs to be given to this problem. Published Unexamined Japanese Patent Application No. S62-217666 discloses as one countermeasure thereagainst a method for manufacturing a MOS type semiconductor device which involves the step of surrounding the source/drain layers of a P-type channel MOS transistor and N-type channel MOS transistor with N-type impurity layers to thereby simultaneously decrease the above-mentioned effects.
Meanwhile, in recent years, there has been a tendency to decrease the level of the drive voltage in view of the demand for power consumption reduction. This means that there is an attempt to drive transistors which have hitherto been made to operate, usually, with a drain voltage of 5V with a drain voltage of, for example, 3V or 2.5V.
However, it has been discovered that in cases where a MOS transistor such as that disclosed in the above publication is driven with the above-mentioned low voltage, the threshold voltage level largely varies. To explain by using the FIG. 2 shown P channel type offset/gate structure transistor as an example, as illustrated in FIG. 5, a threshold voltage Vth level difference of approximately 1V is produced between when the drain voltage V.sub.D =-5V and when the drain voltage V.sub.D =-0.1V. When the threshold voltage level varies as mentioned above, since the drain current I.sub.D .varies.(V.sub.G -Vth) where V.sub.G represents the gate voltage, the amount of the current which can be made to flow with the driving voltage largely varies depending upon variations in the threshold voltage level, or the transconductance thereof varies, with the result that the current-driving capacity varies. This raises the problem of limitation of the degree of freedom of circuit-designs.